1. A Novel Test Data Compaction Method with Improved Debug Capabilities of the Signatures;2023 IEEE International Test Conference India (ITC India);2023-07-23
2. Reducing Output Response Aliasing Using Boolean Optimization Techniques;2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS);2023-05-03
3. Test cost reduction through increase in multi-site testing with reduced scan-out pins;2019 IEEE International Test Conference India (ITC India);2019-07
4. On-chip MISR Compaction Technique to Reduce Diagnostic Effort and Test Time;2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID);2019-01
5. ZATPG: SAT-based test patterns generator with zero-aliasing in temporal compaction;Microprocessors and Microsystems;2018-09