On-chip MISR Compaction Technique to Reduce Diagnostic Effort and Test Time-Reference-Cited by-同舟云学术

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On-chip MISR Compaction Technique to Reduce Diagnostic Effort and Test Time

Published:2019-01 Issue: Volume: Page:
ISSN:
Container-title:2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID)
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Author:

Shenoy Jaidev,Ockunzzi Kelly,Singh Virendra,Kamal Kushal

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8698529/8710751/08711234.pdf?arnumber=8711234

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Novel Test Data Compaction Method with Improved Debug Capabilities of the Signatures;2023 IEEE International Test Conference India (ITC India);2023-07-23

2. A Systematic Method to Generate Effective STLs for the In-Field Test of CAN Bus Controllers;Electronics;2022-08-09

3. Test cost reduction through increase in multi-site testing with reduced scan-out pins;2019 IEEE International Test Conference India (ITC India);2019-07

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