1. Fast algorithms for static compaction of sequential circuit test vectors;hsiao;Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125),1997
2. ROTCO: a reverse order test compaction technique
3. COMPACTEST: a method to generate compact test sets for combinational circuits
4. On static test compaction and test pattern ordering for scan designs;lin;Proceedings International Test Conference 2001 (Cat. No.01CH37260),2001
5. The EPFL combinational benchmark suite;amarù;International Workshop on Logic Synthesis,2015