Codesign of NoC and Cache Organization for Reducing Access Latency in Chip Multiprocessors-Reference-Cited by-同舟云学术

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Codesign of NoC and Cache Organization for Reducing Access Latency in Chip Multiprocessors

Published:2012-06 Issue:6 Volume:23 Page:1038-1046
ISSN:1045-9219
Container-title:IEEE Transactions on Parallel and Distributed Systems
language:
Short-container-title:IEEE Trans. Parallel Distrib. Syst.

Author:

Abousamra A.,Jones A. K.,Melhem R.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Signal Processing

Link

http://xplorestaging.ieee.org/ielx5/71/6189836/06030871.pdf?arnumber=6030871

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A smart protocol-level task mapping for energy efficient traffic on network-on-chip;Microprocessors and Microsystems;2019-03

2. A Diffusional Schedule for Traffic Reducing on Network-on-Chip;2018 5th IEEE International Conference on Cyber Security and Cloud Computing (CSCloud)/2018 4th IEEE International Conference on Edge Computing and Scalable Cloud (EdgeCom);2018-06

3. A Spatial and Temporal Locality-Aware Adaptive Cache Design With Network Optimization for Tiled Many-Core Architectures;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2017-09

4. Reactive circuits: Dynamic construction of circuits for reactive traffic in homogeneous CMPs;Journal of Parallel and Distributed Computing;2016-09

5. Analysis of network-on-chip topologies for cost-efficient chip multiprocessors;Microprocessors and Microsystems;2016-05

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