Subject
Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software
Reference27 articles.
1. Codesign of NoC and cache organization for reducing access latency in chip multiprocessors;Abousamra;IEEE Trans. Parallel Distrib. Syst.,2012
2. Poster: Fly-over: a light-weight distributed power-gating mechanism for energy-efficient networks-on-chip;Boyapati,2016
3. Reducing cache coherence traffic with a NUMA-aware runtime approach;Caheny;IEEE Trans. Parallel Distrib. Syst.,2018
4. E. Carara, A. Mello, F. Moraes, Communication models in networks-on-chip, in: Proceedings of the RSP, Washington, DC, USA, 2007, pp. 57–60. doi:10.1109/RSP.2007.17.
5. E. Carvalho, N. Calazans, F. Moraes, Heuristics for dynamic task mapping in NoC-based heterogeneous MPSoCs, in: Proceedings of the 18th IEEE/IFIP International Workshop on Rapid System Prototyping RSP 2007, 2007, pp. 34–40.
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献