1. Codesign of NoC and cache organization for reducing access latency in chip multiprocessors;Abousamra;IEEE Trans. Parallel Distrib. Syst.,2012
2. Deja-vu switching for multiplane NoCs;Abousamra,2012
3. Achieving predictable performance through better memory controller placement in many-core CMPs;Abts,2009
4. Garnet: A detailed on-chip network model inside a full-system simulator;Agarwal,2009
5. In-network coherence filtering: Snoopy coherence without broadcasts;Agarwal,2009