Dual-Phase Tapped-Delay-Line Time-to-Digital Converter With On-the-Fly Calibration Implemented in 40 nm FPGA-Reference-Cited by-同舟云学术

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Dual-Phase Tapped-Delay-Line Time-to-Digital Converter With On-the-Fly Calibration Implemented in 40 nm FPGA

Published:2016-02 Issue:1 Volume:10 Page:231-242
ISSN:1932-4545
Container-title:IEEE Transactions on Biomedical Circuits and Systems
language:
Short-container-title:IEEE Trans. Biomed. Circuits Syst.

Author:

Won Jun Yeon,Kwon Sun Il,Yoon Hyun Suk,Ko Guen Bae,Son Jeong-Whan,Lee Jae Sung

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Biomedical Engineering

Link

http://xplorestaging.ieee.org/ielx7/4156126/7416019/7057685.pdf?arnumber=7057685

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