Design of a high-precision time-to-digital converter in an Elitestek Ti60 field-programmable-gate-array

Author:

He Zongwu12ORCID,Wen Xincheng3ORCID,Wang Jian12ORCID,Ma Qingli4ORCID,Yin Zejie1

Affiliation:

1. State Key Laboratory of Particle Detection and Electronics, Department of Modern Physics, University of Science and Technology of China 1 , Hefei 230026, China

2. Deep Space Exploration Laboratory 2 , Hefei 230088, China

3. National Synchrotron Radiation Laboratory, University of Science and Technology of China 3 , Hefei 230029, China

4. College of Electronic Countermeasure, National University of Defense Technology 4 , Hefei 230037, China

Abstract

The time-to-digital converter (TDC) implemented in a field-programmable-gate-array has garnered widespread attention due to its flexibility and high-performance capabilities. However, issues such as non-uniformity, the bubble in the tapped delay line, and the presence of certain ultra-wide delay units can significantly compromise the precision and nonlinearity of the TDC. In this paper, we propose a high-precision TDC in an Elitestek Ti60 FPGA, effectively eliminating the adverse effects of non-uniformity, the bubble, and certain ultra-wide delay units. The TDC is constructed with a 318-stage delay chain and operates at a low system clock frequency of 150 MHz. The least significant bit (LSB) of the TDC is 21.92 ps. The differential nonlinearity (DNL) is between (−0.976, 1.615) LSB and the integral nonlinearity (INL) is between (−1.446, 2.678) LSB. The TDC achieves a root-mean-square error of 14.783 ps when utilized for measuring various time intervals.

Funder

National Natural Science Foundation of China

Publisher

AIP Publishing

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