RESURF Region Variation Induced Current Crowding Effect on HV p-LDMOS
Author:
Affiliation:
1. Vanguard International Semiconductor Corp.,DE Department,HsinChu City,Taiwan
2. National Yang Ming Chiao Tung University,Department of Electrical and Computer Eng.,HsinChu City,Taiwan
3. Richtek Technology Corp.,ESD Department,ChuPei City,Taiwan
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10248978/10248979/10249061.pdf?arnumber=10249061
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2. The influence of NBL layout and LOCUS space on component ESD and system level ESD for HV-LDMOS;lee;IEEE Proc Int Symp on Power Semi Dev & ICs (ISPSD),2007
3. The positive trigger voltage lowering effect for latch-up;lee;Proc IEEE Int Symp Phys and Failure Anal Integr Circuits,2004
4. Tunable Holding-Voltage High Voltage ESD Devices
5. A Combination of Implant Shadow and Skin Effects Leading to HV Devices Failure during the ESD Event
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1. A Combination of Implant Shadow and Skin Effects Leading to HV Devices Failure during the ESD Event;2023 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA);2023-07-24
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