Forward Body Bias Technique in DRAM Peripheral Transistor at Cryogenic Temperature for Quantum Computing Applications
Author:
Affiliation:
1. Pohang University of Science and Technology (POSTECH),Department of Electrical Engineering,Pohang,Republic of Korea,37673
2. Samsung Electronics,Memory Division,Hwaseong,Republic of Korea,18448
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10102927/10102928/10102979.pdf?arnumber=10102979
Reference12 articles.
1. Transistor Reliability Characterization for Advanced DRAM with HK+MG & EUV process technology
2. Cryogenic Characteristics of Multinanoscales Field-Effect Transistors
3. Device and Circuit Cryogenic Operation for Low Temperature Electronics;balestra;Boston,2001
4. Investigation of DC Hot-Carrier Degradation at Elevated Temperatures for n-Channel Metal–Oxide–Semiconductor Field-Effect-Transistor of 0.13 µm Technology
5. Hot carrier degradation in semiconductor devices;tibor;Springer,2014
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Cryogenic-Aware Forward Body Biasing in Bulk CMOS;IEEE Electron Device Letters;2024-02
2. Cryogenic Body Bias Effect in DRAM Peripheral and Buried-Channel-Array Transistor for Quantum Computing Applications;IEEE Access;2024
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