A 6.7–11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS-Reference-Cited by-同舟云学术

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A 6.7–11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS

Published:2018-10 Issue:10 Volume:53 Page:2982-2993
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Park Kwanseo^ORCID,Bae Woorham^ORCID,Lee Jinhyung^ORCID,Hwang Jeongho^ORCID,Jeong Deog-Kyoon^ORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/8470270/08453909.pdf?arnumber=8453909

Cited by 32 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 1–6.5 Gbps dual-loop CDR design with Coarse-fine Tuning VCO and modified DQFD;Microelectronics Journal;2024-09

2. 1.4-8 Gb/s Low Power Quarter-Rate Single-Loop Referenceless CDR With Unlimited Capture Range;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-09

3. WR-enhanced TDM-PON with nanosecond clock and data recovery and picosecond time synchronization;Journal of Optical Communications and Networking;2024-02-16

4. A 1-6.5 Gbps Dual-Loop Cdr Design with Coarse-Fine Tuning Vco and Modified Dqfd;2024

5. A 0.0035-mm² 0.42-pJ/bit 8–32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased ChargeSharing Integrator, Alexander PFD, and 1-Tap DFE;ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC);2023-09-11

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