An 18.1 mW 50 MHz-BW 76.4 dB-SNDR CTSDM With PVT-Robust VCO Quantizer and Latency-Free Background-Calibrated DAC-Reference-Cited by-同舟云学术

An 18.1 mW 50 MHz-BW 76.4 dB-SNDR CTSDM With PVT-Robust VCO Quantizer and Latency-Free Background-Calibrated DAC

Published:2022-12 Issue:12 Volume:69 Page:4787-4798
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Guo Yuekang¹,Jin Jing¹^ORCID,Liu Xiaoming¹^ORCID,Zhou Jianjun¹^ORCID

Affiliation:

1. School of Microelectronics, Shanghai Jiao Tong University, Shanghai, China

Funder

Chinese National Natural Science Foundation

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture

Link

http://xplorestaging.ieee.org/ielx7/8919/9985434/09839415.pdf?arnumber=9839415

Reference40 articles.

1. A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH With DAC Non-Linearity Tolerance

2. A Continuous-Time 0–3 MASH ADC Achieving 88 dB DR With 53 MHz BW in 28 nm CMOS

3. A 1-GS/s 20 MHz-BW Capacitive-Input Continuous-Time $\Delta\Sigma$ ADC Using a Novel Parasitic Pole-Mitigated Fully Differential VCO

4. A 74.5-dB Dynamic Range 10-MHz BW CT-ΔΣ ADC With Distributed-Input VCO and Embedded Capacitive-π Network in 40-nm CMOS

5. A phase domain excess loop delay compensation technique with latency optimized phase selector for VCO-based continuous-time $\Delta\Sigma$ ADC;guo;Proc IEEE Int Symp Circuits Syst (ISCAS),2021

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3. A LUT-based Background Linearization Technique for VCO-based ADC Employing $K_{\text{VCO}}-\text{Locked}-\text{Loop}$;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21