A 1-GS/s 20 MHz-BW Capacitive-Input Continuous-Time $\Delta\Sigma$ ADC Using a Novel Parasitic Pole-Mitigated Fully Differential VCO-Reference-Cited by-同舟云学术

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A 1-GS/s 20 MHz-BW Capacitive-Input Continuous-Time $\Delta\Sigma$ ADC Using a Novel Parasitic Pole-Mitigated Fully Differential VCO

Published:2019-01 Issue:1 Volume:2 Page:1-4
ISSN:2573-9603
Container-title:IEEE Solid-State Circuits Letters
language:
Short-container-title:IEEE Solid-State Circuits Lett.

Author:

Mukherjee Abhishek^ORCID,Gandara Miguel,Xu Biying,Li Shaolan,Shen Linxiao,Tang Xiyuan,Pan David,Sun Nan

Funder

National Science Foundation

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

https://ieeexplore.ieee.org/ielaam/8011414/8718885/8693795-aam.pdf

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Analysis of VCO-Based Continuous-Time ΣΔ ADCs Using a Subset of Phases as the Feedback Signal;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-06

2. A 70dB SNDR 20MHz-BW VCO-Based CT Sturdy MASH Delta-Sigma Modulator with Robust Quantization Error Extraction;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

3. Mixed-Order Correlated Dual-Loop Sturdy MASH CT-$\Delta \Sigma $ Modulator With Distributed Signal Feed-In and VCO Quantizer;IEEE Journal of Solid-State Circuits;2024

4. An 18.1 mW 50 MHz-BW 76.4 dB-SNDR CTSDM With PVT-Robust VCO Quantizer and Latency-Free Background-Calibrated DAC;IEEE Transactions on Circuits and Systems I: Regular Papers;2022-12

5. Time Based and VCO-ADCs from a Signal Processing Perspective;Time-encoding VCO-ADCs for Integrated Systems-on-Chip;2022

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