A Continuous-Time 0–3 MASH ADC Achieving 88 dB DR With 53 MHz BW in 28 nm CMOS-Reference-Cited by-同舟云学术

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A Continuous-Time 0–3 MASH ADC Achieving 88 dB DR With 53 MHz BW in 28 nm CMOS

Published:2014-12 Issue:12 Volume:49 Page:2868-2877
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Dong Yunzhi,Yang William,Schreier Richard,Sheikholeslami Ali,Korrapati Sudhir

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/6963535/06955864.pdf?arnumber=6955864

Cited by 55 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Mixed-Order Correlated Dual-Loop Sturdy MASH CT-$\Delta \Sigma $ Modulator With Distributed Signal Feed-In and VCO Quantizer;IEEE Journal of Solid-State Circuits;2024

2. A 10MHz-BW 85dB-DR CT 0-4 Mash Delta-Sigma Modulator Achieving +5dBFS MSA;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-12

3. A Two-Channel Time-Interleaved Continuous-Time Third-Order CIFF-Based Delta-Sigma Modulator;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-12

4. Bandpass Sigma–Delta Modulation: The Path toward RF-to-Digital Conversion in Software-Defined Radio;Chips;2023-03-02

5. High-Speed and High-Performance Continuous-Time ADCs for Automotive Receivers;IEEE Open Journal of the Solid-State Circuits Society;2023

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