A 10MHz-BW 85dB-DR CT 0-4 Mash Delta-Sigma Modulator Achieving +5dBFS MSA-Reference-Cited by-同舟云学术

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A 10MHz-BW 85dB-DR CT 0-4 Mash Delta-Sigma Modulator Achieving +5dBFS MSA

Published:2023-12 Issue:12 Volume:70 Page:4781-4792
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Tan Gaofeng¹,Qin Xinyu¹,Liu Yan¹^ORCID,Guo Mingqiang²^ORCID,Sin Sai-Weng²,Wang Guoxing¹^ORCID,Lian Yong³^ORCID,Qi Liang¹^ORCID

Affiliation:

1. Department of Micro-Nano Electronics, Shanghai Jiao Tong University, Shanghai, China

2. State-Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macau, China

3. Department of Electrical Engineering and Computer Science, York University, Toronto, ON, Canada

Funder

National Natural Science Foundation of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture

Link

http://xplorestaging.ieee.org/ielx7/8919/10363413/10217346.pdf?arnumber=10217346

Reference24 articles.

1. A 4.5 mW CT Self-Coupled $\Delta\Sigma$ Modulator With 2.2 MHz BW and 90.4 dB SNDR Using Residual ELD Compensation

2. Wideband and Low-Power Delta-Sigma ADCs: State of the Art, Trends and Implementation Examples

3. A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH $\Delta \Sigma $ Modulator With Multirate Opamp Sharing

4. A 5GS/s 360MHz-BW 68dB-DR Continuous-Time 1-1-1 Filtering MASH ΔΣ ADC in 40nm CMOS

5. A Multi-Rate Hybrid DT/CT Mash ΔΣ Modulator with High Tolerance to Noise Leakage

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1. Comparative Study for Different Loop-Filter Architectures of 2x Time-Interleaved CT DSM;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. A 2.3-ppm/℃ High-Order Compensated Bandgap Reference With Low-Cost Current Trimming;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

3. Oversampling ADC: A Review of Recent Design Trends;IEEE Access;2024

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