A 372 μW 10 kHz-BW 109.2 dB-SNDR Nested Delta-Sigma Modulator Using Hysteresis-Comparison MSB-Pass Quantization-Reference-Cited by-同舟云学术

A 372 μW 10 kHz-BW 109.2 dB-SNDR Nested Delta-Sigma Modulator Using Hysteresis-Comparison MSB-Pass Quantization

Published:2023-09 Issue:9 Volume:58 Page:2554-2563
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Guo Yuekang¹,Jin Jing¹^ORCID,Liu Xiaoming¹^ORCID,Zhou Jianjun¹^ORCID

Affiliation:

1. State Key Laboratory of Radio Frequency Heterogeneous Integration, Shanghai Jiao Tong University, Shanghai, China

Funder

National Key Research and Development Program of China

National Natural Science Foundation of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/10229945/10092527.pdf?arnumber=10092527

Reference31 articles.

1. A 72 dB-DR 465 MHz-BW Continuous-Time 1-2 MASH ADC in 28 nm CMOS

2. A 0.8-V 230-$\mu$W 98-dB DR Inverter-Based $\Sigma \Delta$ Modulator for Audio Applications

3. A 47.5 MHz BW 4.7 mW 67 dB SNDR ringamp based discrete-time delta sigma ADC;santana;Proc IEEE European Solid-State Circuits Conf (ESSCIRC),2021

4. A 0.0375 mm2 203.5?W 108.8 dB DR DT single-loop DSM audio ADC using a single-ended ring-amplifier-based integrator in 180 nm CMOS;lee;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2022

5. An 18.1 mW 50 MHz-BW 76.4 dB-SNDR CTSDM With PVT-Robust VCO Quantizer and Latency-Free Background-Calibrated DAC

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