A −40-dBc Integrated-Phase-Noise 45-GHz Sub-Sampling PLL with 3.9-dBm Output and 2.1% DC-to-RF Efficiency-Reference-Cited by-同舟云学术

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A −40-dBc Integrated-Phase-Noise 45-GHz Sub-Sampling PLL with 3.9-dBm Output and 2.1% DC-to-RF Efficiency

Published:2019-06 Issue: Volume: Page:
ISSN:
Container-title:2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)
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Author:

Lee Sangyeop,Takano Kyoya,Hara Shinsuke,Dong Ruibing,Amakawa Shuhei,Yoshida Takeshi,Fujishima Minoru

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8700146/8701725/08701745.pdf?arnumber=8701745

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Comparative Analysis of Phase Locked Loop with Different Phase Frequency Detectors using 90nm Technology;2023 Global Conference on Information Technologies and Communications (GCITC);2023-12-01

2. A 25.8-GHz Integer-N CPPLL Achieving 60-fs rms Jitter and Robust Lock Acquisition Based on a Time–Amplifying Phase–Frequency Detector;IEEE Transactions on Microwave Theory and Techniques;2023-11

3. A 0.6-V 41.3-GHz Power-Scalable Sub-Sampling PLL in 55-nm CMOS DDC;IEICE Transactions on Electronics;2023-10-01

4. An Overview on the Low-Jitter Millimeter-Wave Frequency Synthesizer;2023 16th UK-Europe-China Workshop on Millimetre Waves and Terahertz Technologies (UCMMT);2023-08-31

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