A 25.8-GHz Integer-N CPPLL Achieving 60-fs rms Jitter and Robust Lock Acquisition Based on a Time–Amplifying Phase–Frequency Detector
Author:
Affiliation:
1. School of Electrical Science and Engineering, University of Electronic Science and Technology of China, Chengdu, China
Funder
National Natural Science Foundation of China
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Radiation
Link
http://xplorestaging.ieee.org/ielx7/22/10310034/10122243.pdf?arnumber=10122243
Reference34 articles.
1. A 40 GHz CMOS PLL With −75-dBc Reference Spur and 121.9-fsrms Jitter Featuring a Quadrature Sampling Phase-Frequency Detector
2. An 8.55–17.11-GHz DDS FMCW Chirp Synthesizer PLL Based on Double-Edge Zero-Crossing Sampling PD With 51.7-fsrms Jitter and Fast Frequency Hopping
3. Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector
4. A 2.4-GHz Reference-Sampling Phase-Locked Loop That Simultaneously Achieves Low-Noise and Low-Spur Performance
5. A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter
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