A 40 GHz CMOS PLL With −75-dBc Reference Spur and 121.9-fsrms Jitter Featuring a Quadrature Sampling Phase-Frequency Detector
Author:
Affiliation:
1. School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore
Funder
Singapore Ministry of Education Academic Research Fund Tier 2
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Radiation
Link
http://xplorestaging.ieee.org/ielx7/22/9749140/09716774.pdf?arnumber=9716774
Reference27 articles.
1. A —244-dB FOM High-Frequency Piezoelectric Resonator-Based Cascaded Fractional-N PLL With Sub-ppb-Order Channel-Adjusting Technique
2. A W-Band Low-Noise PLL With a Fundamental VCO in SiGe for Millimeter-Wave Applications
3. A 28-nm 75-fsrms Analog Fractional-$N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction
4. A Low-Jitter Low-Phase-Noise 10-GHz Sub-Harmonically Injection-Locked PLL With Self-Aligned DLL in 65-nm CMOS Technology
5. A 2.4–3.6-GHz Wideband Subharmonically Injection-Locked PLL With Adaptive Injection Timing Alignment Technique
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