An 8.55–17.11-GHz DDS FMCW Chirp Synthesizer PLL Based on Double-Edge Zero-Crossing Sampling PD With 51.7-fs<sub>rms</sub> Jitter and Fast Frequency Hopping-Reference-Cited by-同舟云学术

An 8.55–17.11-GHz DDS FMCW Chirp Synthesizer PLL Based on Double-Edge Zero-Crossing Sampling PD With 51.7-fs_rms Jitter and Fast Frequency Hopping

Published:2022-03 Issue:3 Volume:30 Page:267-276
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Xiao Jinhai¹,Liang Ning¹,Chen Bingwen¹,Liu Maliang¹^ORCID

Affiliation:

1. Shaanxi Key Laboratory of Integrated Circuits and Systems, School of Microelectronics, Xidian University, Xi’an, China

Funder

National Natural Science Foundation of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/9726527/09681064.pdf?arnumber=9681064

Reference34 articles.

1. Analysis of Ranging Precision in an FMCW Radar Measurement Using a Phase-Locked Loop

2. Noise in Homodyne FMCW radar systems and its effects on ranging precision

3. A 940 MHz-bandwidth $28.8~\mu\text{s}$ -period 8.9 GHz chirp frequency synthesizer PLL in 65 nm CMOS for X-band FMCW radar applications;yeo;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2016

4. A self-calibrated 16 GHz subsampling-PLL-based 30s fast chirp FMCW modulator with 1.5 GHz bandwidth and 100 kHz rms error;shi;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2019

5. A Study of Phase Noise and Frequency Error of a Fractional-N PLL in the Course of FMCW Chirp Generation

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3. Impact of Receiver Thermal Noise and PLL RMS Jitter in Radar Measurements;IEEE Transactions on Instrumentation and Measurement;2024

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