A 0.6-V 41.3-GHz Power-Scalable Sub-Sampling PLL in 55-nm CMOS DDC
Author:
Affiliation:
1. Hiroshima University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/transele/E106.C/10/E106.C_2022CTS0001/_pdf
Reference17 articles.
1. [1] B. Razavi, “Jitter-power trade-offs in PLLs,” IEEE Trans. Circuits Syst. I, vol.68, no.4, pp.1381-1387, April 2021. 10.1109/tcsi.2021.3057580
2. [2] S. Ikeda, S.-Y. Lee, H. Ito, N. Ishihara, and K. Masu, “A 0.52-V 5.7-GHz low noise sub-sampling PLL with dynamic threshold MOSFET,” Proc. IEEE A-SSCC, pp.365-368, Nov. 2014. 10.1109/asscc.2014.7008936
3. [3] S. Ikeda, S.Y. Lee, H. Ito, N. Ishihara, and K. Masu, “A 0.5V 5.96-GHz PLL with amplitude-regulated current-reuse VCO,” IEEE Microwave Wireless Compon. Lett., vol.27, no.3, pp.302-303, March 2017. 10.1109/lmwc.2017.2662001
4. [4] Z. Zhang et al., “A 0.65-V 12-16-GHz sub-sampling PLL with 56.4-fsrms integrated jitter and -256.4-dB FoM,” IEEE J. Solid-State Circuits, vol.55, no.6, pp.1665-1683, June 2020. 10.1109/JSSC.2020.2967562
5. [5] K. Fujita, Y. Torii, M. Hori, J. Oh, L. Shifren, P. Ranade, M. Nakagawa, K. Okabe, T. Miyake, K. Ohkoshi, M. Kuramae, T. Mori, T. Tsuruta, S. Thompson, and T. Ema, “Advanced channel engineering achieving aggressive reduction of VT variation for ultra-low-power applications,” Proc. IEEE IEDM, pp.32.3.1-32.3.4, Dec. 2011. 10.1109/iedm.2011.6131657
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