Junction capacitance reduction due to self-aligned pocket implantation in elevated source/drain NMOSFETs-Reference-Cited by-同舟云学术

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Junction capacitance reduction due to self-aligned pocket implantation in elevated source/drain NMOSFETs

Published:2001 Issue:9 Volume:48 Page:1969-1974
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Miura N.,Abe Y.,Sughihar K.,Oishi T.,Furukawa T.,Nakahata T.,Shiozawa K.,Maruno S.,Tokuda Y.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx5/16/20433/00944184.pdf?arnumber=944184

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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4. Low thermal budget selective epitaxial growth for formation of elevated source/drain MOS transistors;Journal of Crystal Growth;2004-03

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