A Physical Model for Bulk Gate Insulator Trap Generation During Bias-Temperature Stress in Differently Processed p-Channel FETs
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/9332190/09316806.pdf?arnumber=9316806
Cited by 19 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A physics-based TCAD framework for NBTI;Solid-State Electronics;2023-04
2. A Generic Trap Generation Framework for MOSFET Reliability—Part I: Gate Only Stress–BTI, SILC, and TDDB;IEEE Transactions on Electron Devices;2023
3. Modeling of Classical Channel Hot Electron Degradation in n-MOSFETs Using TCAD;IEEE Transactions on Electron Devices;2022-07
4. A Method to Isolate Intrinsic HCD and NBTI Contributions Under Self Heating During Varying VG/VD Stress in GAA Nanosheet PFETs;IEEE Transactions on Electron Devices;2022-07
5. Decoupling of NBTI and Pure HCD Contributions in p-GAA SNS FETs Under Mixed VG/VD Stress;2022 IEEE International Reliability Physics Symposium (IRPS);2022-03
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