Modeling of Classical Channel Hot Electron Degradation in n-MOSFETs Using TCAD
Author:
Affiliation:
1. Department of Electrical Engineering, IIT Bombay, Mumbai, India
Funder
Synopsys Inc.
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/9802454/09782460.pdf?arnumber=9782460
Reference47 articles.
1. Predictive Hot-Carrier Modeling of n-Channel MOSFETs
2. TCAD Simulation of Hot-Carrier and Thermal Degradation in STI-LDMOS Transistors
3. Insight into the relationship between hot electron degradation and substrate current in sub-0.1 μm technologies
4. Determination of threshold energy for hot electron interface state generation
5. Evidence for a Composite Interface State Generation Mode in the CHE-Stressed Deep-Submicrometer n-MOSFET
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1. Impact of Lightly Doped Drain on Hot Carrier Degradation Variability in N-FETs and SRAM Cells;2024 IEEE International Reliability Physics Symposium (IRPS);2024-04-14
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3. A Generic Framework for MOSFET Reliability—Part II: Gate and Drain Stress—HCD;IEEE Transactions on Electron Devices;2024-01
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5. Compensation of Hot Carrier Degradation Enabled by Forward Back Bias in π-GAA-π MOSFET;IEEE Journal of the Electron Devices Society;2023
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