A Method to Isolate Intrinsic HCD and NBTI Contributions Under Self Heating During Varying VG/VD Stress in GAA Nanosheet PFETs
Author:
Affiliation:
1. Department of Electrical Engineering, IndianInstitute of Technology Bombay (IIT Bombay), Mumbai, India
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/9802454/09773285.pdf?arnumber=9773285
Reference30 articles.
1. BAT Framework Modeling of Dimension Scaling in FinFETs and GAA-SNS FETs
2. A SPICE Compatible Compact Model for Process and Bias Dependence of HCD in HKMG FDSOI MOSFETs
3. A Review of Hot Carrier Degradation in n-Channel MOSFETs—Part I: Physical Mechanism
4. A Review of Hot Carrier Degradation in n-Channel MOSFETs—Part II: Technology Scaling
5. Predictive Hot-Carrier Modeling of n-Channel MOSFETs
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3. A TCAD to SPICE Framework for Isolation of BTI and HCD in GAA-SNS FETs and to Estimate Impact on RO Under Normal and Overclocking Conditions;2024 IEEE International Reliability Physics Symposium (IRPS);2024-04-14
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