A Generic Trap Generation Framework for MOSFET Reliability—Part I: Gate Only Stress–BTI, SILC, and TDDB-Reference-Cited by-同舟云学术

A Generic Trap Generation Framework for MOSFET Reliability—Part I: Gate Only Stress–BTI, SILC, and TDDB

Published:2023 Issue: Volume: Page:1-12
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Mahapatra Souvik¹^ORCID,Ansari Aseer¹^ORCID,Bisht Arnav Shaurya¹,Choudhury Nilotpal¹^ORCID,Parihar Narendra¹^ORCID,Chatterjee Payel¹,Gholve Prasad¹^ORCID,Tiwari Ravi¹^ORCID,Kumar Satyam¹^ORCID,Samadder Tarun¹^ORCID

Affiliation:

1. Department of Electrical Engineering, Indian Institute of Technology Bombay (IIT Bombay), Mumbai, India

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/4358746/10189086.pdf?arnumber=10189086

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