A 6.15–10.9 Gb/s 0.58 pJ/Bit Reference-Less Half-Rate Clock and Data Recovery With “Phase Reset” Scheme-Reference-Cited by-同舟云学术

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A 6.15–10.9 Gb/s 0.58 pJ/Bit Reference-Less Half-Rate Clock and Data Recovery With “Phase Reset” Scheme

Published:2022-02 Issue:2 Volume:69 Page:634-644
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Xiao Wenbo^ORCID,Huang Qiwei^ORCID,Mosalam Hamed^ORCID,Zhan Chenchang^ORCID,Li Zhiqun^ORCID,Pan Quan^ORCID

Funder

National Natural Science Foundation of China

Natural Science Foundation of Guangdong Province

Science and Technology Plan of Shenzhen

Research and Development Program in Key Areas of Guangdong Province

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8919/9694631/09585315.pdf?arnumber=9585315

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 1–6.5 Gbps dual-loop CDR design with Coarse-fine Tuning VCO and modified DQFD;Microelectronics Journal;2024-09

2. Fractionally-Spaced Equalizers as Clock and Data Recovery Loops;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-07

3. Design of a Low-Jitter 5.4 Gbps Half-Rate Clock and Data Recovery Circuit for eDP Application;2024 10th International Conference on Applied System Innovation (ICASI);2024-04-17

4. High Logic Density Cyclic Redundancy Check and Forward Error Correction Logic Sharing Encoding Circuit for JESD204C Controller;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

5. A 1-6.5 Gbps Dual-Loop Cdr Design with Coarse-Fine Tuning Vco and Modified Dqfd;2024

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