Fractionally-Spaced Equalizers as Clock and Data Recovery Loops-Reference-Cited by-同舟云学术

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Fractionally-Spaced Equalizers as Clock and Data Recovery Loops

Published:2024-07 Issue:7 Volume:71 Page:3002-3015
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Ryu Sigang¹^ORCID,Kim Jaeha²^ORCID,Raychowdhury Arijit³^ORCID

Affiliation:

1. Department of Electrical and Electronic Engineering, Korea Aerospace University, Goyang-si, Gyeonggi-do, South Korea

2. School of Electrical Engineering and Computer Science, Inter-University Semiconductor Research Center, Seoul National University, Seoul, South Korea

3. School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/8919/10575936/10521884.pdf?arnumber=10521884

Reference22 articles.

1. An 80 mW 40 Gb/s 7-TapT/2-Spaced Feed-Forward Equalizer in 65 nm CMOS

2. A 1.4-Vppd 64-Gb/s PAM-4 Transmitter with 4-Tap Hybrid FFE Employing Fractionally-Spaced Pre-Emphasis and Baud-Spaced De-Emphasis in 28-nm CMOS

3. A 0.0071-mm2 10.8pspp-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis

4. A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS

5. A Five-Tap Delay-Line-Based Feed-Forward-Equalizer for 200-Gb/s Wireline Receiver in 28-nm CMOS

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