Analysis and Design of a Sub-Sampling PLL of Low Phase Noise and Low Reference Spur-Reference-Cited by-同舟云学术

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Analysis and Design of a Sub-Sampling PLL of Low Phase Noise and Low Reference Spur

Published:2024-08 Issue:8 Volume:71 Page:3597-3607
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Xu Hao¹^ORCID,Ji Shujiang¹^ORCID,Wang Yizhuo¹,Lin Xinyi¹^ORCID,Min Hao¹^ORCID,Yan Na¹^ORCID

Affiliation:

1. State Key Laboratory of Integrated Chip and Systems, Institute of Microelectronics, Fudan University, Shanghai, China

Funder

National Key Research and Development Programs

Program of Shanghai Academic Research Leader

Project of Ministry of Education (MOE) Innovation Platform

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/8919/10618913/10489983.pdf?arnumber=10489983

Reference26 articles.

1. A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by $N ^{2}$

2. A 2.2GHz sub-sampling PLL with 0.16psrms jitter and −125dBc/Hz in-band phase noise at 700µW loop-components power

3. Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector

4. Spur-reduction techniques for PLLs using sub-sampling phase detection

5. 25.2 A 2.2GHz −242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture

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