25.2 A 2.2GHz −242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture
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IEEE
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http://xplorestaging.ieee.org/ielx7/7054075/7062838/07063115.pdf?arnumber=7063115
Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Analysis and Design of a Sub-Sampling PLL of Low Phase Noise and Low Reference Spur;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-08
2. A Millimeter-Wave ADPLL With Reference Oversampling and Third-Harmonic Extraction Featuring High FoMjitter-N;IEEE Solid-State Circuits Letters;2021
3. A 0.65-V 12-16-GHz Sub-Sampling PLL With 56.4-fsrms Integrated Jitter and -256.4-dB FoM;IEEE Journal of Solid-State Circuits;2020
4. A 2.02–2.87-GHz −249-dB FoM 1.1-mW Digital PLL Exploiting Reference-Sampling Phase Detector;IEEE Solid-State Circuits Letters;2020
5. Sub-Sampling PLL For Millimeter Wave Applications: An Overview;2019 IEEE MTT-S International Microwave Conference on Hardware and Systems for 5G and Beyond (IMC-5G);2019-08
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