Spur-reduction techniques for PLLs using sub-sampling phase detection
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx5/5428240/5433812/05433841.pdf?arnumber=5433841
Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Analysis and Design of a Sub-Sampling PLL of Low Phase Noise and Low Reference Spur;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-08
2. A 0.02mm2Sub-Sampling PLL with Spur Reduction Technique in 90nm CMOS Technology;2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT);2023-04-17
3. A Cascaded Mode-Switching Sub-Sampling PLL With Quadrature Dual-Mode Voltage Waveform-Shaping Oscillator;IEEE Transactions on Circuits and Systems I: Regular Papers;2021-06
4. A 2.2-GHz 3.2-mW DTC-Free Sampling $\Delta\Sigma$ Fractional-$N$ PLL With −110-dBc/Hz In-Band Phase Noise and −246-dB FoM and −83-dBc Reference Spur;IEEE Transactions on Circuits and Systems I: Regular Papers;2019-09
5. A 2.1-GHz Third-Order Cascaded PLL With Sub-Sampling DLL and Clock-Skew-Sampling Phase Detector;IEEE Transactions on Circuits and Systems I: Regular Papers;2018-07
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