A 0.02mm<sup>2</sup>Sub-Sampling PLL with Spur Reduction Technique in 90nm CMOS Technology-Reference-Cited by-同舟云学术

A 0.02mm²Sub-Sampling PLL with Spur Reduction Technique in 90nm CMOS Technology

Published:2023-04-17 Issue: Volume: Page:
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Container-title:2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT)
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Author:

Cheng Sheng-Jen¹,Qiu You-Rong¹,Hong Chung-Hung²,Liu Wei-Yi³,Li Chia Hsuan⁴,Chen Chung-Ping¹

Affiliation:

1. Graduate Institute of Electronics Engineering, National Taiwan University,Taipei,Taiwan,10617

2. Kidney Research Center,Chang Gung Memorial Hospital,Taoyuan,Taiwan,33333

3. Graduate Institute of Biomedical Electronics and Bioinformatics, National Taiwan University,Taipei,Taiwan,10617

4. Fu Jen Catholic University,Department of Physics,New Taipei,Taiwan,242062

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10133934/10133941/10134274.pdf?arnumber=10134274

Reference9 articles.

1. A Sub-Sampling-Assisted Phase-Frequency Detector for Low-Noise PLLs With Robust Operation Under Supply Interference

2. A 0.026mm2 5.3mW 32-to-2000MHz Digital Fractional-N Phase Locked-Loop Using a Phase-Interpolating Phase-to-Digital Converter;jang;IEEE ISSCC Dig Tech Papers,2013

3. A Ring-VCO- Based Sub-Sampling PLL CMOS Circuit with ?119 dBc/Hz Phase Noise and 0.73 ps Jitter;sogo;Proc ESSCIRC,0

4. A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by $N ^{2}$

5. A 0.0049mm2 2.3GHz Sub- Sampling Ring-Oscillator PLL with Time-Based Loop Filter Achieving ?236.2dB Jitter-FOM;chuang;IEEE ISSCC Dig Tech Papers,2017

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