A 2.2GHz sub-sampling PLL with 0.16psrms jitter and −125dBc/Hz in-band phase noise at 700µW loop-components power
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IEEE
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http://xplorestaging.ieee.org/ielx5/5552635/5560242/05560323.pdf?arnumber=5560323
Cited by 31 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Analysis and Design of a Sub-Sampling PLL of Low Phase Noise and Low Reference Spur;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-08
2. A 27.2–31.2 GHz 92-fs rms Integrated Jitter, Fractional-N Subsampling PLL Using Phase Rotating Technique in 65-nm CMOS;IEEE Transactions on Microwave Theory and Techniques;2023-12
3. A 2.4-GHz Ring-VCO-Based Sub-Sampling PLL With a −70-dBc Reference Spur by Adopting a Capacitor-Multiplier-Based Sub-Sampling DLL;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-09
4. A 2.4-GHz Sub-Sampling PLL With an Adaptive and No Power Contribution FLL Achieving 103.58 fs rms Jitter and −257.8 dB FOM;IEEE Microwave and Wireless Components Letters;2022-05
5. A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push–Pull SS-PD and a Fast-Locking FLL Achieving −82.2-dBc REF Spur and −255-dB FOM;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2022-02
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