A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push–Pull SS-PD and a Fast-Locking FLL Achieving −82.2-dBc REF Spur and −255-dB FOM-Reference-Cited by-同舟云学术

A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push–Pull SS-PD and a Fast-Locking FLL Achieving −82.2-dBc REF Spur and −255-dB FOM

Published:2022-02 Issue:2 Volume:30 Page:238-242
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Yang Zunsong^ORCID,Chen Yong^ORCID,Yuan Jia,Mak Pui-In^ORCID,Martins Rui P.^ORCID

Funder

Science and Technology Development Fund, Macau SAR

Guangzhou Science and Technology Innovation and Development of Special Funds

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/9705196/09651530.pdf?arnumber=9651530

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