A 6-GHz 78-fs<sub>RMS</sub> Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM-Reference-Cited by-同舟云学术

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A 6-GHz 78-fs_RMS Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving −92-dBc Reference Spur and −258-dB FOM

Published:2024-05 Issue:5 Volume:34 Page:548-551
ISSN:2771-9588
Container-title:IEEE Microwave and Wireless Technology Letters
language:
Short-container-title:IEEE Microw. Wireless Tech. Lett.

Author:

Ren Hongyu¹^ORCID,Yang Zunsong¹^ORCID,Huang Yunbo²^ORCID,Feng Chaoping¹,Chen Tianle¹,Zhang Xinming¹,Meng Xianghe¹,Yan Weiwei¹,Zhang Weidong¹,Iizuka Tetsuya³^ORCID,Chen Yong²^ORCID,Mak Pui-In²^ORCID,Han Zhengsheng¹^ORCID,Li Bo¹^ORCID

Affiliation:

1. Institute of Microelectronics of the Chinese Academy of Sciences, Beijing, China

2. State-Key Laboratory of Analog and Mixed-Signal VLSI/Institute of Microelectronics, and the Faculty of Science and Technology, Department of ECE, University of Macau, Macau, China

3. Systems Design Laboratory, School of Engineering, The University of Tokyo, Tokyo, Japan

Funder

National Natural Science Foundation of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/9944983/10527217/10478016.pdf?arnumber=10478016

Reference28 articles.

1. Jitter-Power Trade-Offs in PLLs

2. 16.8 A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur

3. A Low-Jitter and Low-Spur Charge-Sampling PLL

4. A 20-GHz PLL With 20.9-fs Random Jitter

5. A Wide-Lock-In-Range and Low-Jitter 12–14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop

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