A 20-GHz PLL With 20.9-fs Random Jitter

Author:

Zhao Yu1ORCID,Forghani Mahdi2ORCID,Razavi Behzad2ORCID

Affiliation:

1. Department of Electrical and Computer Engineering, University of California at Los Angeles, Los Angeles, CA, USA

2. Department of Electrical and Computer Engineering, University of California at Los Angles, Los Angeles, CA, USA

Funder

Realtek Semiconductor

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 20 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Radiation-Hardened 15–22-GHz Frequency Synthesizer in 22-nm FinFET;IEEE Journal of Solid-State Circuits;2024-09

2. A 6 to 12-GHz Fractional-N Frequency Synthesizer With a Digital Technique to Counter Modulus-Dependent Feedback Divider Delays;IEEE Journal of Solid-State Circuits;2024-09

3. A Fractional-N Sampling PLL With a Merged Constant-Slope DTC and Sampling PD;IEEE Journal of Solid-State Circuits;2024-08

4. A Multireference PLL: Theory and Implementation;IEEE Journal of Solid-State Circuits;2024-07

5. Jitter Minimization of Phase-locked Loops for OFDM-Based Millimeter-Wave Communication Systems with Beam Steering;2024 31st International Conference on Mixed Design of Integrated Circuits and System (MIXDES);2024-06-27

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