16.8 A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur-Reference-Cited by-同舟云学术

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16.8 A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur

Published:2019-02 Issue: Volume: Page:
ISSN:
Container-title:2019 IEEE International Solid- State Circuits Conference - (ISSCC)
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Author:

Yang Zunsong,Chen Yong,Yang Shiheng,Mak Pui-In,Martins Rui P.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8656625/8662285/08662364.pdf?arnumber=8662364

Cited by 76 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 21.8–41.6-GHz Low Jitter and High FoMj Fast-Locking Subsampling PLL With Dead Zone Automatic Controller;IEEE Transactions on Microwave Theory and Techniques;2024-09

2. Analysis and Design of a Sub-Sampling PLL of Low Phase Noise and Low Reference Spur;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-08

3. A Multireference PLL: Theory and Implementation;IEEE Journal of Solid-State Circuits;2024-07

4. A 45-fs_rms-Jitter, 144-to-162-GHz D-Band Frequency Synthesizer Using a Subsampling PLL and a Harmonic-Boosting Frequency Multiplier;2024 IEEE Radio Frequency Integrated Circuits Symposium (RFIC);2024-06-16

5. Back-Gate Coupling Technique for Phase Error Correction in PLL-Based Quadrature VCOs;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

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