A Multi-Folded MCML for Ultra-Low-Voltage High-Performance in Deeply Scaled CMOS-Reference-Cited by-同舟云学术

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A Multi-Folded MCML for Ultra-Low-Voltage High-Performance in Deeply Scaled CMOS

Published:2020-12 Issue:12 Volume:67 Page:4696-4706
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Palumbo Gaetano^ORCID,Scotti Giuseppe^ORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8919/9275400/09143449.pdf?arnumber=9143449

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design and Analysis of an Ultralow-Voltage Complementary Fold-Interleaved Multiple-Tail Current Mode Logic;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-11

2. A 270 fJ/op 5.8 GHz MOS Current Mode Logic D-Latch for High-Speed Application;2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME);2023-06-18

3. Simple and Accurate Model for the Propagation Delay in MCML Gates;Electronics;2023-06-15

4. MOS Current Mode Logic (MCML) based techniques for D-Flip Flop in 180 nm Technology using LTspice;2023 2nd Edition of IEEE Delhi Section Flagship Conference (DELCON);2023-02-24

5. Design of half adder using integrated leakage power reduction techniques;Materials Today: Proceedings;2022

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