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Design of half adder using integrated leakage power reduction techniques

Published:2022 Issue: Volume:69 Page:576-581
ISSN:2214-7853
Container-title:Materials Today: Proceedings
language:en
Short-container-title:Materials Today: Proceedings

Author:

Bindu Katikala Hima,Pavan Kumar Thatha,Manideep Reddy Bhimavarapu,V.V.Pavan Kumar Bandireddy,Ramana Murthy G.,Dixit Saurav

Funder

Vignan's Foundation for Science, Technology and Research

Publisher

Elsevier BV

Subject

General Medicine

Reference20 articles.

1. Leakage minimization in CMOS VLSI circuits: a brief review;Chaudhury;Design Model. Low Power VLSI Syst.,2016

2. The impact of semiconductor technology scaling on CMOS RF and digital circuits for wireless application;Lee;IEEE Trans. Electron Devices,2005

3. G. Palumbo, G. Scotti. A Multi-Folded MCML for Ultra-Low-Voltage High-Performance in Deeply Scaled CMOS. inIEEE Transactions on Circuits and Systems I: Regular Papers 2020;67:4696-4706. DOI:10.1109/TCSI.2020.3008487.

4. Chip power scaling in recent CMOS technology nodes;Shahidi;IEEE Access,2019

5. Chip power-frequency scaling in 10/7nm node;Oldiges;IEEE Access,2020

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