Leakage Minimization in CMOS VLSI Circuits

Abstract

Ever increasing demand for portable and battery-operated systems has lead to aggressive scaling. While technology scaling facilitates faster and high performance devices, at the same time it causes excessive power dissipation. Leakage power dissipation is now a dominating component of total power consumption in such portable devices. So there is a tremendous need to limit the power dissipation in high density chips which has initiated many innovative techniques to develop in the design of low power circuits and systems. Today's nano-scaled VLSI chips have ultra-thin gate oxide, very low threshold voltage and having short channels. As such leakage power dissipation has emerged as the most challenging issue in VLSI circuit and systems. This Chapter review and compare the state of the art circuit techniques for leakage minimization. It also conceptually classifies the different techniques of leakage minimization. Moreover, a detailed comparison based on trading-offs with other design parameters is also given along with leakage minimization.