Design Implementation and Analysis of Different SRAM Cell Topologies
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9396768/9396772/09396938.pdf?arnumber=9396938
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Low power and noise‐immune 9 T compute SRAM cell design based on differential power generator and Schmitt‐trigger logics with14 nm FinFET technology;International Journal of Circuit Theory and Applications;2024-06-27
2. Memristor-Based Power Efficient 4T3M SRAM Cell;2024 14th International Conference on Electrical Engineering (ICEENG);2024-05-21
3. Optimizing Power Efficiency in SRAM Cells through Memristor-Based Architectures;2024 International Conference on Machine Intelligence and Smart Innovation (ICMISI);2024-05-12
4. Optimized Speed and Power Consumption in a 14T SRAM Bit Cell by Use of Shorted-Gate FinFET;2023 3rd International Conference on Advancement in Electronics & Communication Engineering (AECE);2023-11-23
5. Performance Analysis Of SRAM and Dram in Low Power Application;E3S Web of Conferences;2023
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