Optimized Speed and Power Consumption in a 14T SRAM Bit Cell by Use of Shorted-Gate FinFET-Reference-Cited by-同舟云学术

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Optimized Speed and Power Consumption in a 14T SRAM Bit Cell by Use of Shorted-Gate FinFET

Published:2023-11-23 Issue: Volume: Page:449-453
ISSN:
Container-title:2023 3rd International Conference on Advancement in Electronics & Communication Engineering (AECE)
language:
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Author:

Pandey Mahesh¹,Bansal Shivangi¹,Shah Owais Ahmad²

Affiliation:

1. Noida International University,Department of Electronics & Communication Engineering,Gautam Budh Nagar,India

2. School of Engineering & Technology, K. R. Mangalam University,Gurugram,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10428120/10428096/10428621.pdf?arnumber=10428621

Reference18 articles.

1. Power and Area Efficient Sense Amplifier Based Flip Flop with Wide Voltage and Temperature Upholding for Portable IoT Applications

2. Odd Counter: New Design and Performance Analysis using Carbon Nano Tube Transistors for High Performance Applications

3. Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application

4. DESIGN DIFFERENT TOPOLOGY FOR REDUCTION OF LOW POWER 2:1 MULTIPLEXER USING FINFET IN NANOMETER TECHNOLOGIES

5. Design and Analysis of High Performance Frequency Divider in 32 nm CMOS Technology for Biomedical Applications

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. 9T fast‐write SRAM bit cell with no conflicts for ultra‐low voltage;Electronics Letters;2024-09

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