Simultaneous gate sizing and placement-Reference-Cited by-同舟云学术

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Simultaneous gate sizing and placement

Published:2000 Issue:2 Volume:19 Page:206-214
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Wei Chen ,Cheng-Ta Hseih ,Pedram M.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx5/43/17990/00828549.pdf?arnumber=828549

Cited by 13 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Geometric Programming-Based Automation of Floorplanning in ASIC Physical Design;Lecture Notes in Electrical Engineering;2018-09-01

2. Circuit Analysis Under Process Variations;Timing Performance of Nanometer Digital Circuits Under Process Variations;2018

3. Exploring a homotopy approach for the design of nanometer digital circuits tolerant to process variations;IEICE Electronics Express;2018

4. Optimization of Digital Circuits with Consideration of DF;Simulation and Optimization of Digital Circuits;2018

5. Gate Sizing During Timing-Driven Placement;Lecture Notes in Electrical Engineering;2012-08-08

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