Enabling Next Generation 3D Heterogeneous Integration Architectures on Intel Process-Reference-Cited by-同舟云学术

Enabling Next Generation 3D Heterogeneous Integration Architectures on Intel Process

Published:2022-12-03 Issue: Volume: Page:
ISSN:
Container-title:2022 International Electron Devices Meeting (IEDM)
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Author:

Elsherbini A.¹,Jun K.¹,Liff S.²,Talukdar T.¹,Bielefeld J.¹,Li W.¹,Vreeland R.¹,Niazi H.³,Rawlings B.¹,Ajayi T.³,Tsunoda N.³,Hoff T.¹,Woods C.³,Pasdast G.⁴,Tiagaraj S.⁴,Kabir E.⁵,Shi Y.³,Brezinski W.¹,Jordan R.¹,Ng J.²,Brun X.³,Krisnatreya B.⁶,Liu P.⁵,Zhang B.³,Qian Z.³,Goel M.⁷,Swan J.¹,Yin G.²,Pelto C.²,Torres J.¹,Fischer P.¹

Affiliation:

1. Components Research

2. Logic Technology Development

3. Assembly and Test Technology Development

4. Design Engineering Group

5. Corporate Quality Network

6. Global Sourcing for Equipment and Materials

7. Design Enabling Group, Intel Corporation,USA

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10019319/10019320/10019499.pdf?arnumber=10019499

Reference6 articles.

1. Heterogeneous Integration Using Omni-Directional Interconnect Packaging

2. Enabling Hybrid Bonding on Intel Process

3. Back-End-of-Line Compatible Transistors for Monolithic 3-D Integration

4. Universal Chiplet Interconnect Express (UCIe)®: Building an Open Chiplet Ecosystem;Das Sharma;UCIE whitepaper,2022

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