Monolithic 3D Integration of Vertically Stacked CMOS Devices and Circuits with High-Mobility Atomic-Layer-Deposited In<sub>2</sub>O<sub>3</sub> n-FET and Polycrystalline Si p-FET: Achieving Large Noise Margin and High Voltage Gain of 134 V/V-Reference-Cited by-同舟云学术

Monolithic 3D Integration of Vertically Stacked CMOS Devices and Circuits with High-Mobility Atomic-Layer-Deposited In₂O₃ n-FET and Polycrystalline Si p-FET: Achieving Large Noise Margin and High Voltage Gain of 134 V/V

Published:2022-12-03 Issue: Volume: Page:
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Container-title:2022 International Electron Devices Meeting (IEDM)
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Author:

Tang W.¹,Wang Z.¹,Lin Z.²,Feng L.³,Liu Z.³,Li X.⁴,Ye P. D.²,Guo X.¹,Si M.¹

Affiliation:

1. Shanghai Jiao Tong University,Department of Electronic Engineering,Shanghai,China

2. Purdue University,School of Electrical and Computer Engineering,West Lafayette,IN,USA

3. Hangzhou LinkZill Technology Co., Ltd,Hangzhou,Zhejiang,China

4. Huazhong University of Science and Technology,Wuhan National High Magnetic Field Center and School of Electrical and Electronic Engineering,Wuhan,China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10019319/10019320/10019410.pdf?arnumber=10019410

Reference21 articles.

1. Nanometre-thin indium tin oxide for advanced high-performance electronics

2. Back-End-of-Line Compatible Transistors for Monolithic 3-D Integration

3. Simple Fabrication of a Three-Dimensional CMOS Inverter Using p-Type Poly-Si and n-Type Amorphous Ga–In–Zn–O Thin-Film Transistors

4. Integrating Poly-Silicon and InGaZnO Thin-Film Transistors for CMOS Inverters

5. Complementary Integrated Circuits Based on p-Type SnO and n-Type IGZO Thin-Film Transistors

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