1. Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications
2. Forksheet FETs for advanced CMOS scaling: Forksheet-nanosheet co-Integration and dual work function metal gates at 17nm N-P Space;mertens;2021 Symposium on VLSI Technology Digest of Technical Papers,2021
3. Enabling complimentary FET (CFET) fabrication: selective, isotropic etch of Group IV semiconductors (Conference Presentation)
4. Improved Drying Technology of Single Wafer Tool by Using Hot IPA/DIW
5. Novel forksheet device architecture as ultimate logic scaling device towards 2nm;weckx;IEDM Tech Dig,2019