Forksheet FETs with Bottom Dielectric Isolation, Self-Aligned Gate Cut, and Isolation between Adjacent Source-Drain Structures

Author:

Mertens H.1,Ritzenthaler R.1,Oniki Y.1,Gowda P. Puttarame1,Mannaert G.1,Sebaai F.1,Hikavyy A.1,Rosseel E.1,Dupuy E.1,Peter A.1,Vandersmissen K.1,Radisic D.1,Briggs B.1,Batuk D.1,Geypen J.1,Martinez-Alanis G.1,Seidel F.1,Richard O.1,Chan B.T.1,Mitard J.1,Litta E. Dentoni1,Horiguchi N.1

Affiliation:

1. imec,Leuven,Belgium

Publisher

IEEE

Reference6 articles.

1. Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications

2. Forksheet FETs for advanced CMOS scaling: Forksheet-nanosheet co-Integration and dual work function metal gates at 17nm N-P Space;mertens;2021 Symposium on VLSI Technology Digest of Technical Papers,2021

3. Enabling complimentary FET (CFET) fabrication: selective, isotropic etch of Group IV semiconductors (Conference Presentation)

4. Improved Drying Technology of Single Wafer Tool by Using Hot IPA/DIW

5. Novel forksheet device architecture as ultimate logic scaling device towards 2nm;weckx;IEDM Tech Dig,2019

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1. Investigation of Self-Heating Effect on Forksheet Field-Effect Transistors;2024 Conference of Science and Technology for Integrated Circuits (CSTIC);2024-03-17

2. Two-Dimensional Semiconductors and Transistors for Future Integrated Circuits;ACS Nano;2024-03-08

3. Forksheet Field-Effect Transistors for Area Scaling and Gate-Drain Capacitance Reduction in Nanosheet-based CMOS Technologies;2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM);2024-03-03

4. New structure transistors for advanced technology node CMOS ICs;National Science Review;2024-01-05

5. Effect of Si Separator in Forksheet FETs on Device Characteristics Investigated by Using In-House TCAD Process Emulator and Device Simulator;2023 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD);2023-09-27

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