Fault Diagnosis for Resistive Random-Access Memory and Monolithic Inter-tier Vias in Monolithic 3D Integration
Author:
Affiliation:
1. Duke University,Department of Electrical and Computer Engineering,Durham,NC,USA
Funder
National Science Foundation
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9983856/9983857/09983944.pdf?arnumber=9983944
Reference29 articles.
1. DfT schemes for resistive open defects in RRAMs
2. An efficient march test algorithm for 1 T1R crossbar with complete fault coverage;liu;Electronics Letters,2016
3. A Design-for-Test Solution Based on Dedicated Test Layers and Test Scheduling for Monolithic 3-D Integrated Circuits
4. Testing Open Defects in Memristor-Based Memories
5. RRAM Defect Modeling and Failure Analysis Based on March Test and a Novel Squeeze-Search Scheme
Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Fault Diagnosis for Resistive Random Access Memory and Monolithic Inter-Tier Vias in Monolithic 3-D Integration;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-07
2. Testing and Fault Diagnosis for Multi-level Resistive Random-Access Memory in Monolithic 3D Integration*;2024 IEEE 42nd VLSI Test Symposium (VTS);2024-04-22
3. Device-Aware Diagnosis for Yield Learning in RRAMs;2024 Design, Automation & Test in Europe Conference & Exhibition (DATE);2024-03-25
4. Device-Aware Test for Ion Depletion Defects in RRAMs;2023 IEEE International Test Conference (ITC);2023-10-07
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