Author:
Raju Aradhanan,Sa Sudhir Kumar
Cited by
7 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. An Optimized 4*4 Braun Multiplier for Parallel Processing Architectures with a 3-bit KSA Adder;2023 International Conference on Intelligent Technologies for Sustainable Electric and Communications Systems (iTech SECOM);2023-12-18
2. Efficiency and Speed Trade-Offs in 8-Bit CMOS Adders at 180nm: An In-Depth Examination;2023 IEEE International Conference on Recent Advances in Systems Science and Engineering (RASSE);2023-11-08
3. Performance Evaluation of Adder Architectures for Vedic Multiplier Implementation;2023 4th IEEE Global Conference for Advancement in Technology (GCAT);2023-10-06
4. Efficient Design and Implementation of Matrix Multiplication;2023 1st International Conference on Circuits, Power and Intelligent Systems (CCPIS);2023-09-01
5. VLSI Architectures of Three Operand Binary Adders;2023 International Conference on Advances in Electronics, Communication, Computing and Intelligent Information Systems (ICAECIS);2023-04-19