An Optimized 4*4 Braun Multiplier for Parallel Processing Architectures with a 3-bit KSA Adder-Reference-Cited by-同舟云学术

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An Optimized 4*4 Braun Multiplier for Parallel Processing Architectures with a 3-bit KSA Adder

Published:2023-12-18 Issue: Volume:62 Page:319-324
ISSN:
Container-title:2023 International Conference on Intelligent Technologies for Sustainable Electric and Communications Systems (iTech SECOM)
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Author:

M Sakthimohan¹,G Elizabeth Rani²,P Monisha¹,T Bhuvaneswari³,R Anand⁴,S T Nandhini²

Affiliation:

1. KalaignarKarunanidhi Institute of Technology,Department of ECE,Coimbatore,Tamilnadu,India

2. KalaignarKarunanidhi Institute of Technology,Department of CSE,Coimbatore,Tamilnadu,India

3. Dr. N G P Institute of Technology,Department of ECE,Coimbatore,Tamilnadu,India

4. Nehru Institute of Technology,Department of Aeronautical Engineering,Coimbatore,Tamilnadu,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10434934/10434939/10435221.pdf?arnumber=10435221

Reference30 articles.

1. A Novel Approach to Design Braun Array Multiplier Using Parallel Prefix Adders for Parallel Processing Architectures

2. Design and performance analysis of multipliers using Kogge Stone Adder

3. Design of an Area Efficient Braun Multiplier using High Speed Parallel Prefix Adder in Cadence

4. Implementation of floating point MAC using Residue Number System;Rengasamy;Journal of Theoretical and Applied Information Technology,2014

5. The Cascade Carry Array Multiplier – A Novel Structure of Digital Unsigned Multipliers for Low-Power Consumption and Ultra-Fast Applications

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