Author:
Neeraja B.,Goud R. Sai Prasad
Cited by
3 articles.
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1. Hardware Implementation of the Multiplier Using Argument Bit Grouping;2024 XXVII International Conference on Soft Computing and Measurements (SCM);2024-05-22
2. High-speed adder power reduction and speed improvement using modified kogee stone adder;AIP Conference Proceedings;2024
3. An Optimized 4*4 Braun Multiplier for Parallel Processing Architectures with a 3-bit KSA Adder;2023 International Conference on Intelligent Technologies for Sustainable Electric and Communications Systems (iTech SECOM);2023-12-18